The present invention relates to a semiconductor device and to, for example, a semiconductor device including a Phase Locked Loop (PLL) circuit.
As an example of the Phase Locked Loop (PLL) circuit, dual-path PLL circuits have been suggested (US Patent Publication No. 2013/0222067 and D. Mijuskovic, M. Baye-, T. Chomicz, N. Garg, F. James, P. McEntarfer, and J. Porter, “Cell-based Fully Integrated CMOS Frequency Synthesizers”, IEEE Journal of Solid-State Circuits, Vol. 29, No. 3, pp. 271-279, March 1994, J. Craninckx and M. Steyaert, “A Fully Integrated CMOS DCS-1800 Frequency Synthesizer”, IEEE Journal of Solid-State Circuits, Vol. 33, No. 12, pp. 2054-2065, December 1998.). These PLL circuits are so-called hybrid PLL circuits that each include an analog path and a digital path, and an integration process of an integral path is digitally performed. In the integral path of such a PLL circuit, a Voltage-Controlled Oscillator (VCO) is driven by using a regulator. By using the regulator, Power Supply Rejection Ratio (PSRR) can be improved.